Useless Microoptimizations Homepage Forum

[Useless Microoptimizations]

Normal results for my benchmarks and general explanations are accessible here:
http://cracauer-forum.cons.org/forum/crabench.html

But in this page I added a specialized chart that uses just one CPU with different memory timings and memory frequencies. The chart is cut off closely around the reference point to show differences in detail. If you need the higher values look at the normal crabench page, all these settings are also in the full charts.

The CPU chosen is my X2 3800+ clocked at 2.4 GHz. I also left the 2.4 GHz dual Opteron in. The chart is cut off closely around the reference point to show differences in detail.

Please see http://www.cons.org/cracauer/crabench/memory3.user_narrow.html for a standalone page of this chart (black-n-white version for printing also available).

[Useless Microoptimizations]

This is the chart with only a "few" results.

More different timings are here:
http://www.cons.org/cracauer/crabench/memory.user_narrow.html



(Or visit http://www.cons.org/cracauer/crabench/memoryshort.user_narrow.html to see this chart with text results at the bottom)


This is the chart with only a "few" results.

More different timings are here:
http://www.cons.org/cracauer/crabench/memory.user_narrow.html

[Useless Microoptimizations]

Benchmarks that compare 1T versus 2T command rate

Athlon 64 X2 at 2.4 GHz:
http://www.cons.org/cracauer/crabench/commandrate.user_verynarrow.html

Athlon 64 E6 Venice at 2.55 GHz:
http://www.cons.org/cracauer/crabench/commandrate_venice.user_verynarrow.html

[Useless Microoptimizations]

Benchmarks that compare cache size

Two comparisions:

• Single-CPU: Opteron 939 at 2.55 Ghz versus Venice at same speed with same RAM, timings and mainboard.
  
• Dual-core/CPU: Dual socket 939 Opteron at 2.0 GHz versus a socket 939 X2 at same speed and simulating the Opteron's RAM timings.
  
  

Main results here:
http://www.cons.org/cracauer/crabench/cache.user.html

Except for the Linux kernel and some video encoding the bigger cache is mostly useless. And this is with very slow RAM. If you had both on DDR400 the bigger cache would have even less effect (because a cache miss would be cheaper).

Even if you look at the parallel benchmarks in the wall clock charts you'll see that unless you do lots of plain HTTP transfers it is still pretty useless:
http://www.cons.org/cracauer/crabench/cache.wall.html


BTW, the reason why the Linux kernel benefits from 1024 KB cache is that the include file structure in Linux is so insane that loading and compiling even small C files blows the 512 KB CPU cache when it expands include files. The FreeBSD kernel with much more compact and less nested include files behaves like all the other programs.

[Useless Microoptimizations]

Chart that focuses on RAM bandwidth

My X2 at 2.5 GHz, RAM at 208, 250 and 312 MHz, trying to keep good timings at each.

Chart with CPU time used:
http://www.cons.org/cracauer/crabench/memory2.user_narrow.html

Same chart, but wall clock time so that you can see whether it speeds up parallel benchmarks and throughput:
http://www.cons.org/cracauer/crabench/memory2.wall.html

[Useless Microoptimizations]

I updated the charts linked to above. General cleanup.

Results of my Opteron 939 coming in, see the cache page.

[Useless Microoptimizations]

Opteron 939 around 2.9 GHz.

This chart also contains memory with Winbond BH-5 chips (Geil One BH) at 2-2-2-5 > 250 MHz.

User CPU time:
http://www.cons.org/cracauer/crabench/opteron939.user_narrow.html

Wall clock time (with concurrent tests):
http://www.cons.org/cracauer/crabench/opteron939.wall.html

[Useless Microoptimizations]

I reorganized the charts a little.

The first graphics is now with fewer options.

[Useless Microoptimizations]

Numbers comparing a Core2Duo (E6600) at 3.6 GHz, using 800 and 600 MHz RAM, and also comparing the effect of the 1333 versus 1066 MHz FSB strap:

CPU time:
http://www.cons.org/cracauer/crabench/ddr2.user.html

Wall clock time including multithreading:
http://www.cons.org/cracauer/crabench/ddr2.wall.html